;/**************************************************************************//**
; * @file     startup_R2401.s
; * @brief    CMSIS Core Device Startup File for R2401.
; * @version  V1.00
; * @date     11. April 2025
; *
; * @note
; *
; ******************************************************************************/
;/* Copyright (c) 2025 RJMICRO LIMITED
;
;   All rights reserved.
;   Redistribution and use in source and binary forms, with or without
;   modification, are permitted provided that the following conditions are met:
;   - Redistributions of source code must retain the above copyright
;     notice, this list of conditions and the following disclaimer.
;   - Redistributions in binary form must reproduce the above copyright
;     notice, this list of conditions and the following disclaimer in the
;     documentation and/or other materials provided with the distribution.
;   - Neither the name of RJMICRO nor the names of its contributors may be used
;     to endorse or promote products derived from this software without
;     specific prior written permission.
;   *
;   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
;   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
;   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
;   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
;   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
;   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
;   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
;   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
;   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
;   POSSIBILITY OF SUCH DAMAGE.
;   ---------------------------------------------------------------------------*/
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
    
    

; <h> Stack Configuration
;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>

Stack_Size      EQU     0x00000400

                AREA    STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem       SPACE   Stack_Size
__initial_sp


; <h> Heap Configuration
;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>

Heap_Size       EQU     0x00000C00

                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem        SPACE   Heap_Size
__heap_limit


                PRESERVE8
                THUMB


; Vector Table Mapped to Address 0 at Reset

                AREA    RESET, DATA, READONLY
                EXPORT  __Vectors
                EXPORT  __Vectors_End
                EXPORT  __Vectors_Size

__Vectors       DCD     __initial_sp              ; Top of Stack
                DCD     Reset_Handler             ; Reset Handler
                DCD     NMI_Handler               ; NMI Handler
                DCD     HardFault_Handler         ; Hard Fault Handler
                DCD     MemManage_Handler         ; MPU Fault Handler
                DCD     BusFault_Handler          ; Bus Fault Handler
                DCD     UsageFault_Handler        ; Usage Fault Handler
                DCD     0                         ; Reserved
                DCD     0                         ; Reserved
                DCD     0                         ; Reserved
                DCD     0                         ; Reserved
                DCD     SVC_Handler               ; SVCall Handler
                DCD     DebugMon_Handler          ; Debug Monitor Handler
                DCD     0                         ; Reserved
                DCD     PendSV_Handler            ; PendSV Handler
                DCD     SysTick_Handler           ; SysTick Handler

                ; External Interrupts

                DCD     eDIAG_LEVEL0_IRQHandler       ;  0: eDIAG_LEVEL0
                DCD     eDIAG_LEVEL1_IRQHandler       ;  1: eDIAG_LEVEL1
                DCD     RCC_IRQHandler                ;  2: RCC
                DCD     eDIAG_OC_IRQHandler           ;  3: eDIAG_OC
                DCD     FMC0_IRQHandler               ;  4: FMC0
                DCD     FMC1_IRQHandler               ;  5: FMC1
                DCD     TIM0_IRQHandler               ;  6: TIM0
                DCD     TIM1_IRQHandler               ;  7: TIM1
                DCD     TIM2_IRQHandler               ;  8: TIM2
                DCD     0                             ;  9: Reserved
                DCD     WWDG_IRQHandler               ; 10: WWDG
                DCD     LIN_IRQHandler                ; 11: LIN
                DCD     ADC0_IRQHandler               ; 12: ADC0
                DCD     ADC1_IRQHandler               ; 13: ADC1
                DCD     SPI0_IRQHandler               ; 14: SPI0
                DCD     SPI1_IRQHandler               ; 15: SPI1
                DCD     eCAP_IRQHandler               ; 16: eCAP
                DCD     ePWM_BRK_UP_TRG_COM_IRQHandler; 17: ePWM_BRK_UP_TRG_COM
                DCD     ePWM_CC_IRQHandler            ; 18: ePWM_CC
                DCD     eDIAG_CMP_IRQHandler          ; 19: eDIAG_CMP
                DCD     CAN_IRQ0_IRQHandler           ; 20: CAN_IRQ0
                DCD     IWDG_IRQHandler               ; 21: IWDG
                DCD     GPIOA_IRQHandler              ; 22: GPIOA
                DCD     GPIOB_IRQHandler              ; 23: GPIOB
                DCD     GPIOC_IRQHandler              ; 24: GPIOC
                DCD     DMA_CH0_IRQHandler            ; 25: DMA_CH0
                DCD     DMA_CH1_2_IRQHandler          ; 26: DMA_CH1_2
                DCD     DMA_CH3_6_IRQHandler          ; 27: DMA_CH3_6
                DCD     0                             ; 28: Reserved
                DCD     CAN_IRQ1_IRQHandler           ; 29: CAN_IRQ1
                DCD     0                             ; 30: Reserved
                DCD     0                             ; 31: Reserved
__Vectors_End

__Vectors_Size  EQU     __Vectors_End - __Vectors

                AREA    |.text|, CODE, READONLY


; Reset Handler

Reset_Handler   PROC
                EXPORT  Reset_Handler             [WEAK]
                IMPORT  SystemInit
                IMPORT  __main
                LDR     R0, =SystemInit
                BLX     R0
                LDR     R0, =__main
                BX      R0
                ENDP

; Macro to define default exception/interrupt handlers.
; Default handler are weak symbols with an endless loop.
; They can be overwritten by real handlers.
                MACRO
                Set_Default_Handler  $Handler_Name
$Handler_Name   PROC
                EXPORT   $Handler_Name             [WEAK]
                B        .
                ENDP
                MEND

; Dummy Exception Handlers (infinite loops which can be modified)
				Set_Default_Handler NMI_Handler
				Set_Default_Handler HardFault_Handler
				Set_Default_Handler MemManage_Handler
				Set_Default_Handler BusFault_Handler
				Set_Default_Handler UsageFault_Handler
				Set_Default_Handler SVC_Handler
				Set_Default_Handler DebugMon_Handler
				Set_Default_Handler PendSV_Handler
				Set_Default_Handler SysTick_Handler


				Set_Default_Handler eDIAG_LEVEL0_IRQHandler       ;  0
				Set_Default_Handler eDIAG_LEVEL1_IRQHandler       ;  1
				Set_Default_Handler RCC_IRQHandler                ;  2
				Set_Default_Handler eDIAG_OC_IRQHandler           ;  3
				Set_Default_Handler FMC0_IRQHandler               ;  4
				Set_Default_Handler FMC1_IRQHandler               ;  5
				Set_Default_Handler TIM0_IRQHandler               ;  6
				Set_Default_Handler TIM1_IRQHandler               ;  7
				Set_Default_Handler TIM2_IRQHandler               ;  8
				Set_Default_Handler WWDG_IRQHandler               ; 10
				Set_Default_Handler LIN_IRQHandler                ; 11
				Set_Default_Handler ADC0_IRQHandler               ; 12
				Set_Default_Handler ADC1_IRQHandler               ; 13
				Set_Default_Handler SPI0_IRQHandler               ; 14
				Set_Default_Handler SPI1_IRQHandler               ; 15
				Set_Default_Handler eCAP_IRQHandler               ; 16
				Set_Default_Handler ePWM_BRK_UP_TRG_COM_IRQHandler; 17
				Set_Default_Handler ePWM_CC_IRQHandler            ; 18
				Set_Default_Handler eDIAG_CMP_IRQHandler          ; 19
				Set_Default_Handler CAN_IRQ0_IRQHandler           ; 20
				Set_Default_Handler IWDG_IRQHandler               ; 21
				Set_Default_Handler GPIOA_IRQHandler              ; 22
				Set_Default_Handler GPIOB_IRQHandler              ; 23
				Set_Default_Handler GPIOC_IRQHandler              ; 24
				Set_Default_Handler DMA_CH0_IRQHandler            ; 25
				Set_Default_Handler DMA_CH1_2_IRQHandler          ; 26
				Set_Default_Handler DMA_CH3_6_IRQHandler          ; 27
				Set_Default_Handler CAN_IRQ1_IRQHandler           ; 29
                ALIGN


; User Initial Stack & Heap

                IF      :DEF:__MICROLIB

                EXPORT  __initial_sp
                EXPORT  __heap_base
                EXPORT  __heap_limit

                ELSE

                IMPORT  __use_two_region_memory
                EXPORT  __user_initial_stackheap

__user_initial_stackheap PROC
                LDR     R0, =  Heap_Mem
                LDR     R1, =(Stack_Mem + Stack_Size)
                LDR     R2, = (Heap_Mem +  Heap_Size)
                LDR     R3, = Stack_Mem
                BX      LR
                ENDP

                ALIGN

                ENDIF


                END
     